This invention relates to semi-conductor manufacturing processes, and more particularly to an aerosol process for inspecting free standing structures.
As minimum semiconductor design feature sizes decrease from 90 nm to 65 nm to 40 nm, structures such as those created by traditional lithography-etching become mechanically less and less stable. Unstable structures will cause defects that result in electrical opens or shorts, preventing circuit operation. The use of new ultra short wavelength lithography/resist systems makes across chip line width variation (ACLV) control difficult, such that lines within a chip, or portions of such lines, can easily be 10% smaller than the average. The necessity for on-mask corrections further compounds the problem, because imperfect optical proximity correction (OPC), which compensates a design for lithographic image variation due to local environment, actually can make the local line variation worse.
The industry has relied predominately on electrical and critical dimension measurements via scanning electron microscopy (SEM) to determine average line widths across a chip or wafer. Realistically, measurements are preformed on structures in nested, semi-nested and isolated local environments that mimic the product chip to obtain a fairly good understanding the line widths on the product chip.
Ideally, all local environments should be measured on a product chip or wafer to ensure an accurate understanding of line width. Since this is not feasible, line width variations and/or failures may exist and will ultimately be detected in the product through electrical characterization and subsequent failure analysis. This procedure, however, is a costly, time consuming, and resource intensive solution.
Thus there is a need in the art for an improved method for identifying specific regions on a wafer or chip where free standing structures of a specific width, such as poly-Si gates, resist trenches, or trenches in a low K material such as SiLK, fail to maintain structural integrity.